View TDA4886A_521788.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

INTEGRATED CIRCUITS
DATA SHEET
TDA4886A 140 MHz video controller with I2C-bus
Product specification File under Integrated Circuits, IC02 1998 Dec 04
Philips Semiconductors
Product specification
140 MHz video controller with I2C-bus
CONTENTS 1 2 3 4 5 6 7 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.10 8 9 10 11 12 12.1 12.2 13 14 15 15.1 15.2 15.3 15.4 16 17 18 FEATURES GENERAL DESCRIPTION ORDERING INFORMATION QUICK REFERENCE DATA BLOCK DIAGRAM PINNING FUNCTIONAL DESCRIPTION Signal input stage (input clamping, blanking and clipping) Electronic potentiometer stages Output stage Pedestal blanking Output clamping, feedback references and DAC outputs Clamping and blanking pulses On Screen Display (OSD) Subcontrast adjustment, contrast modulation and beam current limiting I2C-bus control I2C-bus data buffer LIMITING VALUES THERMAL CHARACTERISTICS CHARACTERISTICS I2C-BUS PROTOCOL TEST AND APPLICATION INFORMATION Test boards Recommendations for building the application board INTERNAL CIRCUITRY PACKAGE OUTLINE SOLDERING Introduction to soldering through-hole mount packages Soldering by dipping or by solder wave Manual soldering Suitability of through-hole mount IC packages for dipping and wave soldering methods DEFINITIONS LIFE SUPPORT APPLICATIONS PURCHASE OF PHILIPS I2C COMPONENTS
TDA4886A
1998 Dec 04
2
Philips Semiconductors
Product specification
140 MHz video controller with I2C-bus
1 FEATURES
TDA4886A
* 140 MHz pixel rate * 2.8 ns rise time, 3.8 ns fall time * I2C-bus control * I2C-bus data buffer for synchronization of adjustments * Grey scale tracking * On Screen Display (OSD) mixing with 50 MHz pixel rate * OSD contrast * Negative feedback for DC-coupled cathodes * Especially for AC-coupled cathodes - Black level adaptable to kind of post amplifier - Internal positive feedback - DAC outputs for black level restoration. * Integrated black level storage capacitors * Beam current limiting * Subcontrast/contrast modulation * Pedestal blanking * Sync clipping. 3 ORDERING INFORMATION TYPE NUMBER TDA4886A PACKAGE NAME SDIP24 DESCRIPTION plastic shrink dual in-line package; 24 leads (400 mil) VERSION SOT234-1 2 GENERAL DESCRIPTION The TDA4886A is a monolithic integrated RGB pre-amplifier for colour monitor systems (e.g. 15" and 17") with I2C-bus control and OSD. In addition to bus control, beam current limiting and contrast modulation are possible. The signals are amplified in order to drive commonly used video modules or discrete solutions. Individual black level control with negative feedback from the cathode (DC coupling) or gradually adaptable black level control with positive feedback and 3 DAC outputs for external cut-off control (AC coupling) is possible. With special advantages the circuit can be used in conjunction with the TDA485X monitor deflection IC family.
1998 Dec 04
3
Philips Semiconductors
Product specification
140 MHz video controller with I2C-bus
4 QUICK REFERENCE DATA SYMBOL VP IP VP1,2,3 IP1,2,3 Vi(b-w) Vo(b-w) Vo(b-w)(max) Vo Vbl(DC) Vbl(AC) PARAMETER supply voltage (pin 7) supply current (pin 7) channel supply voltage (pins 21, 18 and 15) channel supply current (pins 21, 18 and 15) input voltage (black-to-white value; pins 6, 8 and 10) nominal output voltage swing (black-to-white value; pins 22, 19 and 16) maximum output voltage swing (black-to-white value; pins 22, 19 and 16) output voltage level (pins 22, 19 and 16) typical reference black level for DC coupling control bit FPOL = 0 (pins 22, 19 and 16) typical reference black level for AC coupling control bit FPOL = 1 and (pins 22, 19 and 16) PEDST = 0 BLH2 = 0; BLH1 = 0 BLH2 = 0; BLH1 = 1 BLH2 = 1; BLH1 = 0 BLH2 = 1; BLH1 = 1 Io(sink) Io(source) B tr(o) tf(o) dVo ct(f) CC TRo GC BC peak output sink current peak output source current bandwidth video rise time at signal outputs (pins 22, 19 and 16) video fall time at signal outputs (pins 22, 19 and 16) overshoot at signal outputs (pins 22, 19 and 16) crosstalk suppression by frequency contrast control related to nominal contrast tracking of output signals for contrast variation from maximum to minimum gain control related to maximum gain brightness control (typical black level voltage change related to nominal output signal amplitude) minimum rise time f = 50 MHz - - - - nominal contrast; maximum gain maximum contrast; maximum gain CONDITIONS MIN. 7.6 - 7.6 - - - - 0.05 0.5
TDA4886A
TYP. 8.0 21 8.0 21 0.7 2.8 4.54 - -
MAX. 8.8 25 8.8 25 1.0 - -
UNIT V mA V mA V V V
VP - 1 V 2.5 V
0.77 1.01 1.25 1.49 - - 165 2.8 3.8 17 - - 0.0 - -
- - - - 20 - - - - 30 - +4.2 0.5 0 +30
V V V V mA mA MHz ns ns % dB dB dB dB %
during fast signal transients - during fast signal transients -40 -3 dB (small signal) - - - 8 25 -28 - -7.3 -10
Vo(OSD)(max) maximum OSD output voltage swing related maximum OSD contrast; to nominal output voltage swing maximum gain (pins 22, 19 and 16) COSD OSD contrast control related to maximum OSD contrast
-
120
-
%
-12
-
0
dB
1998 Dec 04
4
This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ...
dbook, full pagewidth
1998 Dec 04
6 REGISTER PEDST DISO DISV FPOL BLH1 BLH2 LIM 24 VI1 6 INPUT CLAMPING BLANKING VI2 8 INPUT CLAMPING BLANKING
5
Philips Semiconductors
140 MHz video controller with I2C-bus
BLOCK DIAGRAM
SDA SCL 12 13 6 6-BIT DAC 4 4-BIT DAC 6 6 6
6
8
8-BIT DAC 8-BIT DAC 8-BIT DAC
CHANNEL 1 REFERENCE CHANNEL 2 REFERENCE CHANNEL 3 REFERENCE
FPOL
I2C-BUS
6-BIT DAC
6-BIT DAC
6-BIT DAC
6-BIT DAC
8
FPOL
8 SUBCONTRAST CONTRAST MODULATION LIMITING BRIGHTNESS BLANKING
FPOL
TDA4886A
GAIN FPOL
21
VP1
CONTRAST
22
VO1
OSD CONTRAST
BRIGHTNESS PEDESTAL BLANKING 23 18 PEDST FPOL FPOL 19 FB/R1 VP2
CONTRAST
GAIN VO2 PEDESTAL BLANKING 20 PEDST FPOL 15 FB/R2 VP3
5
VI3 10
OSD CONTRAST
BRIGHTNESS
INPUT CLAMPING BLANKING
CONTRAST
GAIN FPOL 16 VO3
OSD CONTRAST
BRIGHTNESS
PEDESTAL BLANKING 17 PEDST 14 FPOL BLH2 BLH1 DISV SUPPLY output clamping FB/R3 GNDX
fast blanking input clamping DISO OSD INPUT INPUT CLAMPING VERTICAL BLANKING 4 5 CLI vertical blanking blanking
BLANKING OUTPUT CLAMPING 11 HFB
1 FBL
2
3
7 VP
9
Product specification
TDA4886A
MHB264
OSD1 OSD2 OSD3
GND
Fig.1 Block diagram.
Philips Semiconductors
Product specification
140 MHz video controller with I2C-bus
6 PINNING PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 DESCRIPTION fast blanking input for OSD insertion OSD input channel 1 OSD input channel 2 OSD input channel 3 input clamping; vertical blanking input signal input channel 1 supply voltage signal input channel 2 ground signal input channel 3 horizontal flyback input (output clamping, blanking) I2C-bus I2C-bus serial data input/output clock input
handbook, halfpage
TDA4886A
SYMBOL FBL OSD1 OSD2 OSD3 CLI VI1 VP VI2 GND VI3 HFB SDA SCL GNDX VP3 VO3 FB/R3 VP2 VO2 FB/R2 VP1 VO1 FB/R1 LIM
FBL 1 OSD1 2 OSD2 3 OSD3 4 CLI 5 VI1 6
24 LIM 23 FB/R1 22 VO1 21 VP1 20 FB/R2 19 VO2
TDA4886A
VP 7 VI2 8 GND 9 VI3 10 HFB 11 SDA 12
MHB265
18 VP2 17 FB/R3 16 VO3 15 VP3 14 GNDX 13 SCL
ground channels 1, 2 and 3 supply voltage channel 3 signal output channel 3 feedback input/reference voltage output channel 3 supply voltage channel 2 signal output channel 2 feedback input/reference voltage output channel 2 supply voltage channel 1 signal output channel 1 feedback input/reference voltage output channel 1 subcontrast, contrast modulation, beam current limiting input
Fig.2 Pin configuration.
1998 Dec 04
6
Philips Semiconductors
Product specification
140 MHz video controller with I2C-bus
7 FUNCTIONAL DESCRIPTION 7.2.3
TDA4886A
GAIN CONTROL (DRIVEN BY I2C-BUS, 6-BIT DAC)
AND GREY SCALE TRACKING
See block diagram (Fig.1) and definition of levels and output signals (see Chapter "Characteristics" notes 1 to 3; Figs 3 to 6). 7.1 Signal input stage (input clamping, blanking and clipping)
The RGB input signals with nominal signal amplitude of 0.7 V are capacitively coupled into the TDA4886A from a low-ohmic source (75 recommended) and actively clamped to an internal DC voltage during signal black level. Because of the high-ohmic input impedance of the TDA4886A the coupling capacitor (which also functions as a storage capacitor between clamping pulses) can be relatively small (10 nF recommended). Very small input currents will discharge the coupling capacitor resulting in black output signals for missing input clamping pulses. Composite signals will not disturb normal operation because a clipping circuit cuts all signal parts below black level. A fast signal blanking stage belongs to the input stage which is driven by several blanking pulses (see Section "Clamping and blanking pulses") and control bit DISV = 1. During the off condition the internal reference black level will be inserted instead of the input signals. 7.2 7.2.1 Electronic potentiometer stages CONTRAST CONTROL (DRIVEN BY I2C-BUS, 6-BIT DAC)
Gain control is used for white point adjustment (correction for different voltage to light amplification of the three colour channels) and therefore individual for the three channels. The video signals related to the reference black level can be gain controlled within a range of typically 7.3 dB. The nominal setting is maximum gain. The video signal is the addition of the contrast controlled input signal and the brightness shift. The gain setting is also valid for OSD signals, thus the complete `grey scale' is effected by gain control. 7.3 Output stage
In the output stage the nominal input signal will be amplified to 2.8 V output colour signal at nominal contrast and maximum gain. The maximum input to output amplification at maximum contrast and gain settings is 16.2 dB. By output clamping the reference black level can be adjusted. In order to achieve fast rise and fall times of the output signals with minimum crosstalk between the channels, each output stage has its own supply voltage pin. 7.4 Pedestal blanking
The input signals related to the internal reference black level can be simultaneously adjusted by contrast control with a control range of typically 32 dB. The nominal contrast setting is defined for 26H (4.2 dB below maximum). 7.2.2 BRIGHTNESS CONTROL (DRIVEN BY I2C-BUS, 6-BIT DAC)
For the video portion the reference black level should correspond to the `extended cut-off voltage' at the cathode. Nevertheless during vertical flyback retrace lines may be visible, though blanking to spot cut-off is useful. With control bit PEDST = 1 the pedestal black level will be adjusted by output clamping instead of the reference black level (see Fig.5). The pedestal black level is more negative than the video black level at minimum brightness setting and the voltage difference to reference black level is fixed. 7.5 Output clamping, feedback references and DAC outputs
With brightness control the video black level will be shifted in relation to the reference black level simultaneously for all three channels. With a negative setting (maximum 10% of nominal signal amplitude) dark signal parts will be lost in ultra black while for positive settings (maximum 30% of nominal signal amplitude) the background will alter from black to grey. The nominal brightness setting (10H) is no shift. The brightness setting is also valid for OSD signals. During blanking and output clamping the video black level will be blanked to reference black level (brightness blanking).
The aim of the output clamping (pins FB/R1, FB/R2 and FB/R3 with control bit FPOL = 0, internal feedback with control bit FPOL = 1) is to set the reference black level of the signal outputs to a value which corresponds to the `extended cut-off voltage' of the CRT cathodes. With a lack of output clamping pulses the integrated storage capacitors will be discharged resulting in output signals going to switch-off voltage. Feedback references are driven by the I2C-bus.
1998 Dec 04
7
Philips Semiconductors
Product specification
140 MHz video controller with I2C-bus
1. Control bit FPOL = 0 The cathode voltage (DC-coupled) is divided by a voltage divider and fed back to the IC. During the output clamping pulse it is compared with an adjustable feedback reference voltage with a range of approximately 5.77 to 4.05 V. Any difference will lead to a reference black level correction (control bit PEDST = 0) or pedestal black level correction (control bit PEDST = 1) by charging or discharging the integrated capacitor which stores the black level information between the output clamping pulses. The DC voltages of the output stages should be designed in such a way that the reference black level/pedestal black level is within the range of 0.5 to 2.5 V. For correct operation it is necessary that there is enough headroom for ultra black signals (negative brightness setting, pedestal black level if control bit PEDST = 1). Any clipping with the video supply voltage at the cathode can disturb the signal rise/fall times or the black level stabilization. 2. Control bit FPOL = 1 For applications with AC-coupled cathodes the signal outputs are fed back internally. During the output clamping pulse they are compared with a feedback reference voltage of approximately 0.75, 1.0, 1.25 or 1.5 V (depending on the values of control bits BLH2 and BLH1). These values ensure a good adaptability to discrete and integrated post amplifiers as well. For black level restoration the DAC outputs (FB/R1, FB/R2 and FB/R3) with a range of approximately 5.77 to 4.05 V can be used. The use of pedestal blanking allows a very simple black level restoration with a DC diode clamp instead of a complicated pulse restoration circuit because the pedestal black level is the most negative output signal. 7.6 Clamping and blanking pulses
TDA4886A
During the vertical blanking pulse at pin CLI signal blanking, brightness blanking and with control bit PEDST = 1 pedestal blanking will be activated. Input clamping pulses during vertical blanking will not switch off blanking. For proper input clamping the input signals have to be at black level during the input clamping pulse. An input pulse at pin HFB (e.g. horizontal flyback pulse) will be scanned with two thresholds. If the input pulse exceeds the first one (typical 1.4 V) signal blanking, brightness blanking and if control bit PEDST = 1 pedestal blanking will be activated. If the input pulse exceeds the second one (typical 3 V) additionally output clamping will be activated. The vertical blanking pulse can also be mixed with the horizontal flyback pulse at pin HFB. 7.7 On Screen Display (OSD)
If the fast blanking input signal at pin FBL exceeds the threshold (typical 1.4 V) the input signals are blanked (signal blanking) and OSD signals are enabled. Then any signal at pins OSD1, OSD2 or OSD3 exceeding the same threshold will create an insertion signal with an amplitude of 120% of the nominal colour signal (approximately 74% of the maximum colour signal). The amplitude can be controlled by OSD contrast (driven by the I2C-bus) with a range of 12 dB. The OSD signals are inserted at the same point as the contrast controlled input signals and will be treated with brightness and gain control like normal input signals. With control bit DISO = 1 the OSD signal insertion and fast blanking (pin FBL) are disabled. 7.8 Subcontrast adjustment, contrast modulation and beam current limiting
The pin CLI of TDA4886A can be directly connected to pin CLBL of e.g. TDA4855 sync processor for input clamping pulses and vertical blanking pulses. The threshold for the input clamping pulse (typical 3 V) is higher than the threshold for the vertical blanking pulse (typical 1.4 V) but there must be no blanking during input clamping. Thus vertical blanking only is enabled if no input clamping is detected. For this reason the input clamping pulse must have rise/fall times faster than 75 ns/V during the transition from 1.2 to 3.5 V and vice versa. The internal vertical blanking pulse will be delayed by typical 270 ns.
The pin LIM is a linear contrast control pin which allows subcontrast setting, contrast modulation and beam current limiting. The maximum contrast is defined by the actual I2C-bus setting. Input signals at pin LIM act on video and OSD signals and do not affect the contrast bit resolution. To achieve brightness uniformity over the screen, scan dependent contrast modulation is possible.
1998 Dec 04
8
Philips Semiconductors
Product specification
140 MHz video controller with I2C-bus
7.9 I2C-bus control 2. Direct mode
TDA4886A
The TDA4886A contains an I2C-bus receiver for several control functions: 1. Contrast control with 6-bit DAC 2. Brightness control with 6-bit DAC 3. OSD contrast control with 4-bit DAC 4. Gain control for each channel with 6-bit DAC 5. Internal feedback reference and external reference voltage control for each channel with 8-bit DAC 6. Control register with control bits BLH2, BLH1, FPOL, DISV, DISO and PEDST. After power-up and after internal power-on reset of the I2C-bus the registers are set to the following values: * Control bit FPOL to logic 1 * Control bits BLH2, BLH1, DISV, DISO and PEDST to logic 0 * All other alignment registers to logic 0 (minimum value for control registers). 7.10 I2C-bus data buffer
Adjustments via the I2C-bus take effect immediately. a) Most significant bit (MSB) of subaddresses is set to logic 0. b) Number of I2C-bus transmissions in direct mode is unlimited. c) Adjustments take effect directly at the end of each I2C-bus transmission. d) Direct mode can be used for all adjustments but large changes of control values may appear as visual disturbances in the picture on the monitor. e) Auto-increment is possible. f) Vertical blanking pulse is not necessary.
1. Buffered mode Adjustments via the I2C-bus are synchronized with vertical blanking pulse at CLI. a) Most significant bit (MSB) of subaddresses is set to logic 1. b) Only one I2C-bus transmission in buffered mode is accepted before the start of the vertical blanking pulse. Following transmission trials will get no acknowledge. c) Received data is stored in one internal 8-bit buffer. d) Adjustments will take effect with detection of the first vertical blanking pulse after the end of according I2C-bus transmission. e) Waiting for vertical blanking pulse in buffered mode can be interrupted by power-on reset. f) Auto-increment is impossible. g) Buffered mode should be used for user adjustments such as contrast, OSD contrast and brightness while picture on monitor is visible.
1998 Dec 04
9
Philips Semiconductors
Product specification
140 MHz video controller with I2C-bus
8 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL VP VP1, 2, 3 Vi Vext PARAMETER supply voltage (pin 7) supply voltage channels 1, 2 and 3 (pins 21, 18 and 15) input voltage (pins 6, 8 and 10) external DC voltage applied to the following pins: pins 1 to 4 pins 5 and 11 pins 12 and 13 pins 23, 20 and 17 pins 22, 19 and 16 pin 24 Io(av) IOM Ptot Tstg Tamb Tj VESD average output current (pins 22, 19 and 16) peak output current (pins 22, 19 and 16) total power dissipation storage temperature operating ambient temperature junction temperature electrostatic handling for all pins machine model human body model Notes 1. No external voltages. 2. Equivalent to discharging a 200 pF capacitor via a 0.75 H inductance ("UZW-B0/FQ-B302"). note 2 note 3 -250 -2000 -0.1 -0.1 -0.1 -0.1 note 1 -0.1 - - - -25 -20 -25 CONDITIONS 0 0 -0.1 MIN.
TDA4886A
MAX. 8.8 8.8 VP VP VP + 0.7 VP VP + 0.7 note 1 VP 20 50 1400 +150 +70 +150 +250 +2000 V V V V V V V V
UNIT
mA mA mW C C C V V
3. Equivalent to discharging a 100 pF capacitor via a 1500 series resistor ("UZW-B0/FQ-A302"). 9 THERMAL CHARACTERISTICS SYMBOL Rth(j-a) PARAMETER thermal resistance from junction to ambient CONDITIONS in free air VALUE 55 UNIT K/W
1998 Dec 04
10
Philips Semiconductors
Product specification
140 MHz video controller with I2C-bus
TDA4886A
10 CHARACTERISTICS All voltages and currents are measured in a dedicated test circuit which is optimized for best high frequency performance; all voltages are measured with respect to GND (pins 9 and 14); VP = VP1, 2, 3 = 8 V (pins 7, 21, 18 and 15); Tamb = 25 C; nominal input signals [0.7 V (p-p) at pins 6, 8 and 10]; nominal colour signals at signal outputs (pins 22, 19 and 16); reference black level (Vrbl) approximately 0.77 V; nominal settings for brightness and contrast; maximum settings for OSD contrast and gain; no subcontrast, modulation of contrast or limiting (V24 5 V); no OSD fast blanking (pin 1 connected to ground); notes 1 to 3; unless otherwise specified. SYMBOL Supplies VP IP VP1,2,3 IP1,2,3 supply voltage (pin 7) supply current (pin 7) channel supply voltage (pins 21, 18 and 15) channel supply current (pins 21, 18 and 15) supply voltage for signal switch off (threshold at pin 7) signal outputs (pins 22, 19 and 16) open-circuit; Vrbl 0.77 V; notes 4 and 5 signal outputs switched to switch-off voltage note 4 7.6 - 7.6 - 8.0 21 8.0 21 8.8 25 8.8 25 V mA V mA PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
VPSO
-
-
7.2
V
Input clamping and vertical blanking input, validation of buffered I2C-bus data (pin 5) V5 input clamping and vertical blanking input signal notes 6 and 7 no vertical blanking, no input clamping vertical blanking, no input clamping input clamping, no vertical blanking I5 input current V5 = 1 V pin 5 connected to ground; note 8 V5 = -0.1 V; note 8 tr/f5 rise/fall time for input clamping pulse, disable for vertical blanking width of input clamping pulse width of vertical blanking pulse for validation of buffered I2C-bus data delay between leading edge of vertical blanking pulse and validation of buffered I2C-bus data leading and trailing edge threshold V5 = 1.4 V; note 7 I2C-bus transmission in buffered mode completed; leading edge threshold V5 = 1.4 V; note 7 note 6; see Fig.7 -0.1 1.6 3.5 - -80 -250 - - - - -0.2 -60 -200 - +1.2 2.6 VP - -30 -100 75 V V V A A A ns/V
tW5 tW5I2C
0.6 10
- -
- -
s s
tI2Cvalid
-
-
2
s
tI2Cdead
dead time of I2C-bus receiver leading edge threshold after synchronizing vertical V5 = 1.4 V; note 7 blanking pulse in case of a completed I2C-bus transmission in buffered mode 11
15
-
-
s
1998 Dec 04
Philips Semiconductors
Product specification
140 MHz video controller with I2C-bus
TDA4886A
SYMBOL tdl5
PARAMETER
CONDITIONS
MIN. -
TYP. 270
MAX. -
UNIT ns
delay between leading edges of V11 < 0.8 V; input pulse with vertical blanking input pulse and 50 ns/V; threshold for rising signal blanking at signal outputs input pulse V5 = 1.4 V; threshold after input clamping pulse V5 = 3 V; VI(b-w) = 0.7 V; see Fig.7 delay between trailing edges of V11 < 0.8 V; input pulse with vertical blanking input pulse and 50 ns/V; threshold V5 = 1.4 V; see Fig.7 internal blanking pulse
tdt5
-
115
-
ns
Output clamping and blanking input (pin 11) V11 output clamping and blanking input signal note 9 no blanking, no output clamping blanking, no output clamping blanking, output clamping I11 input current V11 = 0.8 V pin 11 connected to ground; note 8 V11 = -0.1 V; note 8 tW11 Vi(b-w)6,8,10 II6,8,10 width of output clamping pulse threshold V11 = 3 V Video signal inputs (channel 1: pin 6; channel 2: pin 8; channel 3: pin 10) positive input signal referred to black DC input current no input clamping; VI6,8,10 = VI(clamp)6, 8, 10; Tamb = -20 to +70 C during input clamping; VI6,8,10 = VI(clamp)6,8,10 0.7 V Signal blanking ct(blank) crosstalk suppression from input to output during blanking control bit DISV = 1; f = 80 MHz 20 control bit DISV = 1; f = 120 MHz 10 - - - - dB dB - 0.02 0.7 0.20 1.0 0.35 V A -0.1 2.0 3.5 - -80 -250 1 - - - -0.4 -60 -200 - +0.8 2.6 VP - -30 -100 - V V V A A A s
100
135
170
A
Clipping of negative input signals (measured at signal outputs) Vclipp offset during sync clipping related to nominal colour signal VI6,8,10 = VI(clamp)6,8,10; note 10; see Fig.3 - - 2 %
Contrast control; see Fig.8 and note 11 dC colour signal related to nominal colour signal 3FH (maximum) 26H (nominal) 00H (minimum) Gtrack tracking of output colour signals 3FH to 00H; note 12 of channels 1, 2 and 3 - - - - 4.2 0 -28 0.0 - - - 0.5 dB dB dB dB
1998 Dec 04
12
Philips Semiconductors
Product specification
140 MHz video controller with I2C-bus
TDA4886A
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP. - -
MAX.
UNIT
Fast blanking (pin 1) and OSD signal insertion (channel 1: pin 2; channel 2: pin 3; channel 3: pin 4); note 13 V1 fast blanking input signal no video signal blanking, OSD signal insertion disabled video signal blanking, OSD signal insertion enabled V2,3,4 OSD input signal V1 > 1.7 V no internal OSD signal insertion internal OSD signal insertion tr(OSD) tf(OSD) tg(CO) rise time of OSD colour signals (pins 22, 19 and 16) fall time of OSD colour signals (pins 22, 19 and 16) width of (negative going) OSD signal insertion glitch, leading edge (pins 22, 19 and 16) width of (negative going) OSD signal insertion glitch, trailing edge (pins 22, 19 and 16) overshoot/undershoot of OSD colour signal related to actual OSD output pulse amplitude (pins 22, 19 and 16) maximum OSD colour signal related to nominal colour signal (pins 22, 19 and 16) 10 to 90% amplitude; input pulse with 1.2 ns/V 90 to 10% amplitude; input pulse with 1.2 ns/V identical pulses at fast blanking input (pin 1) and OSD signal inputs (pins 2, 3 and 4) identical pulses at fast blanking input (pin 1) and OSD signal inputs (pins 2, 3 and 4) pulse with 1.2 ns/V at OSD signal inputs (pins 2, 3 and 4) 0 1.7 - - 0 - - - - - 1.1 VP 4 7 6 V V ns ns ns 0 1.7 1.1 VP V V
tg(OC)
0
-
6
ns
dVOSD
-
-
30
%
VOSD(max)
maximum OSD contrast; maximum gain
100
120
140
%
OSD contrast control; see Fig.9 and note 14 dOC OSD colour signal related to maximum OSD colour signal 0FH (maximum) 00H (minimum) - -14 0 -12 - -10 dB dB
Subcontrast adjustment, contrast modulation and beam current limiting (pin 24); see Fig.8 and note 15 V24(nom) V24(start) V24(stop) B24 I24(max) Vbl nominal input voltage starting voltage for contrast and OSD contrast reduction stop voltage for contrast and OSD contrast reduction bandwidth of contrast modulation maximum input current -32 dB below maximum colour signal (contrast setting 3FH) -3 dB V24 = 0 V 3FH (maximum) 10H (nominal) 00H (minimum) pin 24 open-circuit 4.7 4.2 1.5 4 -1.0 5.0 4.5 2.0 - - 5.3 4.8 2.5 - - V V V MHz A
Brightness control; see Fig.10 and notes 16 and 17 difference between black level and reference black level at signal outputs related to nominal colour signal 25 - -12 30 0 -10 35 - -8 % % %
1998 Dec 04
13
Philips Semiconductors
Product specification
140 MHz video controller with I2C-bus
TDA4886A
SYMBOL
PARAMETER
CONDITIONS
MIN. - -8.3 -18
TYP.
MAX. - -6.3 -14
UNIT
Gain control; see Fig.11 and note 18 dG video signal related to video signal at maximum gain 3FH (maximum) 00H (minimum) 0 -7.3 -16 dB dB
Pedestal blanking V22,19,16(PED) difference from pedestal black level to video black level at nominal brightness, measured at signal output pins related to nominal colour signal note 19; see Fig.5 %
Signal outputs (channel 1: pin 22; channel 2: pin 19; channel 3: pin 16) V22,19,16(nom) nominal colour signal nominal contrast; maximum gain; Vi(b-w) = 0.7 V; without load maximum contrast; maximum gain; Vi(b-w) = 0.7 V; without load 2.5 2.8 3.1 V
V22,19,16(max)
maximum colour signal
4.1
4.54
5
V
V22,19,16(min) V22,19,16(top)
switch-off voltage (minimum output voltage level) maximum output voltage level at arbitrary input signals, contrast, brightness and gain adjustments; without load
-
0.05
0.1
V
VP - 2 -
VP - 1 V
R(o)22,19,16 I22,19,16(source)
output resistance maximum source current during fast positive signal transients output voltage V22,19,16 0.77 V; note 20 output voltage V22,19,16 = 6 V; note 20
- -15 -40 3.2 1.6 - 44 -
75 - - 4 2 - - -
- - - - - 20 - 0.6
mA mA mA mA mA dB %
I22,19,16(M)(source) peak source current I22,19,16(sink) maximum sink current (built-in current source)
I22,19,16(M)(sink) S/N D22,19,16(th)
peak sink current signal-to-noise ratio output thermal distortion
during fast negative signal transients note 21 note 22
1998 Dec 04
14
Philips Semiconductors
Product specification
140 MHz video controller with I2C-bus
TDA4886A
SYMBOL G22,19,16(f) tr(22,19,16)
PARAMETER
CONDITIONS
MIN. - -
TYP.
MAX.
UNIT
Frequency response at signal outputs (channel 1: pin 22; channel 2: pin 19; channel 3: pin 16) amplification decrease by frequency response rise time of fast transients f = 165 MHz; Vi(b-w) 0.2 V (small signal) input rise time = 1 ns; 10 to 90% amplitude; nominal colour signal; note 23 input fall time = 1 ns; 90 to 10% amplitude; nominal colour signal; note 23 1.2 2.8 3.0 3.1 dB ns
tf(22,19,16)
fall time of fast transients
-
3.8
4.1
ns
dV22,19,16
overshoot of output signal pulse input rise time = 1 ns; related to actual output pulse nominal colour signal amplitude undershoot of output signal pulse related to actual output pulse amplitude input fall time = 1 ns; nominal colour signal
8
17
30
%
3
13
25
%
Crosstalk at signal outputs (channel 1: pin 22; channel 2: pin 19; channel 3: pin 16) ct(tr) ct(f) transient crosstalk suppression crosstalk suppression by frequency input rise/fall time = 1 ns; note 24 f = 50 MHz f = 100 MHz 10 25 10 - - - - - - dB dB dB
Internal feedback reference voltage; see Fig.12 and note 25 Vref(n) Vref(p) internal reference voltage for negative feedback polarity internal reference voltage for positive feedback polarity FFH (minimum); FPOL = 0 00H (maximum); FPOL = 0 FPOL = 1 BLH2 = 0; BLH1 = 0 BLH2 = 0; BLH1 = 1 BLH2 = 1; BLH1 = 0 BLH2 = 1; BLH1 = 1 0.71 0.95 1.19 1.43 -500 0.77 1.01 1.25 1.49 -200 0.83 1.07 1.31 1.55 -60 V V V V 3.85 5.6 4.05 5.77 4.2 5.9 V V
Output clamping, feedback inputs for DC coupling (channel 1: pin 23; channel 2: pin 20; channel 3: pin 17) I23,20,17(max) maximum input current during output clamping; V11 > 3.5 V; V23,20,17 = 0.5 V; FPOL = 0 PEDST = 0; V11 > 3.5 V; FPOL = 0 PEDST = 1; V11 > 3.5 V; FPOL = 0 PEDST = 0; V11 > 3.5 V; FPOL = 0 PEDST = 1; V11 > 3.5 V; FPOL = 0 FPOL = 0; note 26 nA
V22,19,16(rbl)(min)
minimum reference black level minimum pedestal black level
0.01 0.01 2.4 2.4 -
0.1 0.1 2.8 2.8 -
0.5 0.5 - - 200
V V V V mV
V22,19,16(rbl)(max)
maximum reference black level maximum pedestal black level
Vbl(CRT)
black level variation at CRT
1998 Dec 04
15
Philips Semiconductors
Product specification
140 MHz video controller with I2C-bus
TDA4886A
SYMBOL V22,19,16(bl)(lf)
PARAMETER black level variation between clamping pulses related to nominal colour signal
CONDITIONS FPOL = 0; line frequency = 60 kHz; 10% duty cycle
MIN. -
TYP. 0.25
MAX. 0.5
UNIT %
Output clamping for AC coupling (internal feedback of signal outputs) V22,19,16(rbl) reference black level V11 > 3.5 V; FPOL = 1; PEDST = 0 BLH2 = 0; BLH1 = 0 BLH2 = 0; BLH1 = 1 BLH2 = 1; BLH1 = 0 BLH2 = 1; BLH1 = 1 pedestal black level V11 > 3.5 V; FPOL = 1; PEDST = 1 BLH2 = 0; BLH1 = 0 BLH2 = 0; BLH1 = 1 BLH2 = 1; BLH1 = 0 BLH2 = 1; BLH1 = 1 V22,19,16(bl)(lf) black level variation between clamping pulses related to nominal colour signal FPOL = 1; line frequency = 60 kHz; 10% duty cycle 0.71 0.95 1.19 1.43 - 0.77 1.01 1.25 1.49 0.25 0.83 1.07 1.31 1.55 0.5 V V V V % 0.71 0.95 1.19 1.43 0.77 1.01 1.25 1.49 0.83 1.07 1.31 1.55 V V V V
External reference voltages for AC coupling (FB/R1: pin 23; FB/R2: pin 20; FB/R3: pin 17); see Fig.13 and note 27 V23,20,17 R23,20,17 I23,20,17(sink) I23,20,17(source) external reference voltage output resistance maximum sink current maximum source current FFH (minimum); FPOL = 1 00H (maximum); FPOL = 1 FPOL = 1 FPOL = 1 FPOL = 1 3.85 5.6 - - - - 0.0 3.0 VIL = 0 V VIH = 5 V during acknowledge VOL = 0.4 V -10 -10 0.0 3.0 - - - - 4.05 5.77 100 - -330 - - - - - - - 1.5 3.5 - 1.5 4.2 5.9 - 400 -280 V V A A
I2C-bus inputs (SDA: pin 12; SCL: pin 13); note 28 fSCL VIL VIH IIL IIH VOL I12(ack) Vth(POR)(r) Vth(POR)(f) SCL clock frequency LOW-level input voltage HIGH-level input voltage LOW-level input current HIGH-level input current LOW-level output voltage output current at pin 12 during acknowledge 100 1.5 5.0 - - 0.4 5.0 2.0 - 7.0 - kHz V V A A V mA V V V V
threshold for power-on reset on rising supply voltage falling supply voltage threshold for power-on reset off rising supply voltage falling supply voltage
1998 Dec 04
16
Philips Semiconductors
Product specification
140 MHz video controller with I2C-bus
Notes to the characteristics 1. Definition of levels (see Figs 3 to 5)
TDA4886A
Reference black level: this is the level to which the input level is clamped during the input clamping pulse (V5 > 3.5 V). It is used internally as a reference for the gain settings. It can be observed on the outputs: a) When the input is at black and the brightness setting is nominal (subaddress 01H = 10H) b) During output blanking/clamping (V11 > 3.5 V) if control bit PEDST = 0. Video black level: this is the black level of the actual video. On the input it is still equal to the reference black level. On the output it may deviate from it according to the brightness setting. Contrast setting leaves the video black level unaltered . Gain setting biases the video black level due to its influence on brightness. This is important for correct grey scale tracking. Pedestal black level: this is an ultra black level which deviates from reference black level by a fixed amount. It can be observed on the output during output blanking/clamping (V11 > 3.5 V) if control bit PEDST = 1. Switch-off voltage: this is the lowest signal voltage at outputs. The signals will be switched off by discharging the internal black level storage capacitors if the supply voltage is less than VPSO. Blanking level: this level equals reference black (control bit PEDST = 0) or pedestal black (control bit PEDST = 1). 2. Explanation to black level adjustment: The three reference black levels are aligned correctly when they are made equal to the `extended cut-off levels' of the three cathodes. Full raster and spot cut-off can only be achieved by enabling the pedestal blanking or by applying a negative pulse to the control grid G1. Negative feedback for DC-coupled cathodes (control bit FPOL = 0): the actual blanking level on the outputs depends on the external feedback application for output clamping. The loop will function correctly only if it is within the control range of V22,19,16(rbl)(min) to V22,19,16(rbl)(max). It should be noted that changing control bit PEDST in a given application will not affect the blanking level, but instead shifts the video (and needs re-alignment of the three black levels). Positive feedback for AC-coupled cathodes (control bit FPOL = 1): the feedback loop for output clamping is closed internally. The actual blanking level at the outputs depends on control bits BLH2 and BLH1 only. Four discrete blanking levels between approximately 0.75 and 1.5 V can be chosen. It should be noted that changing control bit PEDST will not affect the blanking level selected by control bits BLH2 and BLH1, but instead shifts the video (and needs re-alignment of the three black levels). 3. Definition of output signals (see Fig.6): Colour signal: all positive voltages referred to black level at signal outputs. Nominal colour signal: colour signal with nominal input signal (0.7 Vb-w), nominal contrast setting and maximum gain setting. Video signal: all positive voltages referred to reference black level at signal outputs. The video signal is the superimposing of the brightness information (Vbl) and the colour signal. 4. The total supply current IP = I7 + I21 + I18 + I15 depends on the supply voltage with a factor of approximately 4.4 mA/V and varies in the temperature range from -20 to +70 C by approximately 5% (V22,19,16 = 0.77 V). 5. The channel supply current depends on the signal output current, the channel supply voltage and the signal output voltage. With Ipx = I21,18,15 at VP1,2,3 = 8 V and V22,19,16 = 0.77 V: mA mA I 21,18,15 I px + I 22,19,16 + 4.4 -------- x ( V P1,2,3 - 8 V ) - 1 -------- x ( V 22, 19, 16 - 0.77 V ) V V
1998 Dec 04
17
Philips Semiconductors
Product specification
140 MHz video controller with I2C-bus
TDA4886A
6. Pin 5 should be used for input clamping and blanking during vertical retrace (signal blanking, brightness blanking and if control bit PEDST = 1 pedestal blanking). With a fast clamping pulse (transition between V5 = 1.2 to 3.5 V and vice versa in less than 75 ns/V) no blanking will occur during input clamping. For 75 ns/V < tr/f5 280 ns/V the generation of the internal vertical blanking pulse is uncertain. For tr/f5 > 280 ns/V the internal blanking pulse will be generated. Pin 5 open-circuited will activate permanent input clamping and undefined blanking. 7. Pin 5 can be used to synchronize all adjustments via the I2C-bus (one by one). In case of a completed I2C-bus transmission in buffered mode only the leading edge of a vertical blanking pulse activates an adjustment. See also Section 7.10. After the adjustment has been activated (validation of buffered I2C-bus data) the I2C-bus will be reset and further transmissions in direct or buffered mode are enabled. I2C-bus transmissions in direct mode need no synchronization pulses. 8. Input voltages less than -0.1 V can produce internal substrate currents which disturb the leakage currents at the signal inputs. An internal protection circuit creates a current for pin voltages of approximately 0 V or less. Feeding clamping/blanking pulses via a resistor of some k protects the pin from negative voltages. 9. Pin 11 should be used for output clamping and/or blanking. Pin 11 open-circuited will activate permanent blanking and output clamping. 10. Composite signals will not disturb normal operations because an internal clipping circuit cuts all signal parts below input reference black level (see Fig.3). 11. Contrast control acts on internal colour signals under I2C-bus control; subaddress 02H (bit resolution 1.6% of contrast range). A 1 A 20 A 1 A 30 A 2 A 30 12. G track = 20 x maximum of log -------- x -------- ; log -------- x -------- ; log -------- x -------- dB A 10 A 2 A 10 A 3 A 20 A 3 An: colour signal output amplitude in channel n = 1, 2 or 3 at any contrast setting. An0: colour signal output amplitude in channel n = 1, 2 or 3 at nominal contrast setting and same gain setting. 13. When OSD fast blanking is active and V2,3,4 are HIGH (V1 > 1.7 V, V2,3,4 > 1.7 V) the OSD colour signals will be inserted in front of the gain potentiometers. This assures a correct grey scale of all video signals. The amplitudes of the inserted OSD signals can be controlled simultaneously by OSD contrast via the I2C-bus. 14. OSD contrast control acts on inserted OSD colour signals under I2C-bus control; subaddress 03H (bit resolution 6.7% of OSD contrast range). 15. This pin can be used for subcontrast setting, beam current limiting and contrast modulation. Both the video and OSD contrast are reduced simultaneously (see Figs 8 and 9). Because of the high-ohmic input impedance the pin should be tied to a voltage of more than 5 V or applied with a capacitor of some nF if not used. 16. Brightness control adds an I2C-bus controlled DC offset to the internal colour signal; subaddress 01H (bit resolution 1.6% of brightness range). 17. The voltage difference between video black level and reference black level is related to the colour signal (see note 3) with nominal 0.7 V (p-p) input signal, at nominal contrast (subaddress 02H = 26H) and for any gain setting. The voltage difference (in Volts) is proportional to the gain setting (grey scale tracking). Therefore Vbl (in percent) is constant for any gain setting. The given values of Vbl are valid only for video black levels higher than the signal output switch-off voltage V22,19,16(min). 18. Gain control acts on video signals and inserted OSD video signals under I2C-bus control; subaddress 04H (channel 1), 05H (channel 2) and 06H (channel 3; bit resolution 1.6% of gain range respectively).
1998 Dec 04
18
Philips Semiconductors
Product specification
140 MHz video controller with I2C-bus
TDA4886A
19. Pedestal blanking produces an ultra black level during blanking and output clamping which is the most negative signal at the signal output pins. The reference black level which should correspond to the `extended cut-off voltage' at the cathodes is approximately V22,19,16(PED) higher (see Fig.5). The use of pedestal blanking with AC-coupled cathodes (control bit FPOL = 1) allows a very simple black level restoration with a DC diode clamp instead of a complicated pulse restoration circuit. 20. DC load currents of signal outputs must not exceed maximum sink currents, otherwise signal distortions may occur. 21. The signal-to-noise ratio is calculated by the formula (range 1 to 120 MHz): peak-to-peak value of the nominal signal output voltage S --- = 20 x log -------------------------------------------------------------------------------------------------------------------------------------------------- dB RMS value of the noise output voltage N 22. Large output currents e.g. I22,19,16(M)(source) lead to signal depending power dissipation in output transistors. Thermal VBE variation is compensated. 23. Following formula can be used to approximately determine the output rise/fall time for any other input rise/fall time: 2 2 2 2 t r/f, measured = t r/f (22,19,16) + t r/f, input - ( 1ns ) 24. Transient crosstalk between any two output pins: a) Input conditions: any channel (channel A) with nominal input signal and 1 ns rise time. The inputs of the other two channels are capacitively coupled to ground (channel B). Gain setting to maximum (3FH). Contrast setting to nominal (26H). No limiting/modulation of contrast (V24 5 V) b) Output conditions: black level set to approximately 0.77 V for each channel at signal outputs. Output signals are VA and VB respectively VA c) Transient crosstalk suppression: ct(tr) = 20 x log ------ dB VB 25. The internal feedback reference voltages are not influenced by the value of control bit PEDST but depend on the individual adjustments via the I2C-bus, the selected feedback polarity (control bit FPOL = 0 or 1) and the selected black level for positive feedback polarity (control bit FPOL = 1 and control bits BLH2 = 0 or 1 and BLH1 = 0 or 1): Control bit FPOL = 0: the internal feedback reference voltage acts under I2C-bus control; subaddress 07H (channel 1), 08H (channel 2) and 09H (channel 3; bit resolution 0.4% of voltage range). Rising values of the data bytes, e.g. 00H to FFH, correspond to rising values of the resulting reference black levels at signal outputs (pins 22, 19 and 16). The internal feedback reference voltages can be measured at feedback inputs (pins 23, 20 and 17) during output clamping (V11 > 3.5 V) in closed feedback loop. The feedback loop remains operative at reference black levels between the specified values of V22,19,16(rbl)(min) and V22,19,16(rbl)(max). Control bit FPOL = 1: the internal feedback reference voltage can be measured at signal outputs (pins 22, 19 and 16) during output clamping (V11 > 3.5 V). By means of control bits BLH2 and BLH1 it is possible to choose one of the four specified values between approximately 0.75 and 1.5 V. This facilitates the adaption to different kinds of post amplifiers. 26. Slow variations of video supply voltage VCRT will be suppressed at the CRT cathode by the clamping feedback loop. A change of VCRT with 5 V leads to a specified change of the cathode voltage. 27. The external reference voltages act under I2C-bus control for control bit FPOL = 1; subaddress 07H (FB/R1), 08H (FB/R2) and 09H (FB/R3; bit resolution 0.4% of voltage range). 28. All adjustments via the I2C-bus can be synchronized with vertical blanking pulse at pin CLI. This is called I2C-bus transmission in buffered mode. The adjustments via the I2C-bus will take effect immediately in the so called direct mode. The timing of I2C-bus transmissions in buffered mode is related to the vertical blanking. See specification of pin 5 (vertical blanking input) and note 7.
1998 Dec 04
19
Philips Semiconductors
Product specification
140 MHz video controller with I2C-bus
TDA4886A
handbook, full pagewidth
input signals
input video signal with syncs at pins 6, 8 and 10
input reference black level
the syncs will be clipped to reference black level internally input clamping pulses at pin 5
blanking/output clamping pulses at pin 11
MHA344
The input video signals have to be on black level during input clamping.
Fig.3 Input signals.
1998 Dec 04
20
Philips Semiconductors
Product specification
140 MHz video controller with I2C-bus
TDA4886A
handbook, full pagewidth pulse, blanking
output clamping pulse at pin 11 blanking signal output signals pins 22, 19 and 16 (1) maximum gain setting, nominal contrast setting, maximum/nominal/minimum brightness setting (2) (3) video black levels at maximum brightness nominal brightness minimum brightness reference black level
switch-off voltage ground
(1) (2) maximum gain setting, maximum brightness setting, maximum/nominal/minimum contrast setting
(3)
video black level (maximum brightness) reference black level
switch-off voltage ground
maximum brightness setting, nominal contrast setting, maximum/minimum gain setting
(1) (3)
video black level (maximum brightness) reference black level
MHB187
switch-off voltage ground
(1) Maximum. (2) Nominal. (3) Minimum.
Fig.4
Definition of levels, function of brightness setting, contrast setting, gain setting, no pedestal blanking (PEDST = 0).
1998 Dec 04
21
Philips Semiconductors
Product specification
140 MHz video controller with I2C-bus
TDA4886A
handbook, full pagewidth blanking pulse,
output clamping pulse at pin 11 blanking signal output signals pins 22, 19 and 16
PEDST = 0 no pedestal blanking (1) maximum gain setting, nominal contrast setting, maximum/minimum brightness setting
(2)
video black levels at maximum brightness minimum brightness reference black level
switch-off voltage ground
PEDST = 1 pedestal blanking maximum gain setting, nominal contrast setting, maximum/minimum brightness setting (1)
(2)
video black levels at maximum brightness minimum brightness reference black level
switch-off voltage ground
pedestal black level
MHB188
(1) Maximum. (2) Minimum.
Fig.5 Output signals without (PEDST = 0) and with pedestal blanking (PEDST = 1).
1998 Dec 04
22
Philips Semiconductors
Product specification
140 MHz video controller with I2C-bus
TDA4886A
handbook, full pagewidth output signals
pins 22, 19 and 16 PEDST = 0 no pedestal blanking maximum gain setting, nominal contrast setting, maximum/minimum brightness setting
colour signals
video signals
video black levels at maximum brightness minimum brightness
reference black level
MHB189
Fig.6 Definition of output signals.
handbook, full pagewidth
3V input pulses at pin 5 trf5 75 ns/V 1.4 V
internal pulse for input clamping tdl5 internal pulse for vertical blanking tdt5 tdl5
MHB190
Fig.7 Timing of pulses at pin 5 and derived internal pulses.
1998 Dec 04
23
Philips Semiconductors
Product specification
140 MHz video controller with I2C-bus
TDA4886A
handbook, full pagewidth
MHB191
4.2 (1)
colour signal amplitude related to nominal colour signal amplitude (dB) 0
(2)
-28 00H 10H 20H 26H
(3)
3FH 30H contrast control data byte
(1) No contrast reduction by subcontrast. (2) Partial contrast reduction by subcontrast. (3) Full contrast reduction by subcontrast.
Fig.8 Contrast control characteristic with subcontrast (equal to contrast modulation and limiting).
handbook, full pagewidth
160 OSD signal amplitude related to nominal colour signal amplitude (%)
maximum colour signal amplitude
MHA351
125
maximum OSD signal amplitude
100
nominal colour signal amplitude (1)
(2)
30 00H
(3) 0FH OSD contrast control data byte
(1) No OSD contrast reduction by subcontrast. (2) Partial OSD contrast reduction by subcontrast. (3) Full OSD contrast reduction by subcontrast.
Fig.9 OSD contrast control characteristic with subcontrast (equal to contrast modulation and limiting).
1998 Dec 04
24
Philips Semiconductors
Product specification
140 MHz video controller with I2C-bus
TDA4886A
handbook, full pagewidth
MHA352
30 difference of video black level and reference black level related to nominal colour signal amplitude (%) 0 (2)
(1)
-10
00H
10H
20H
30H brightness control data byte
3FH
(1) Nominal adjustment. (2) Nominal brightness reference black level.
Fig.10 Brightness control characteristic.
MHA353
handbook, full pagewidth
100
video signal gain related to maximum video signal gain (%) 45
0
00H
10H
20H
30H gain control data byte
3FH
Fig.11 Gain control characteristic.
1998 Dec 04
25
Philips Semiconductors
Product specification
140 MHz video controller with I2C-bus
TDA4886A
handbook, full pagewidth
MHB192
5.77
(1)
internal feedback reference voltage (V) 4.05
(2) (3) (4) (5)
1.49 1.25 1.01 0.77 0 00H
20H
40H
60H
80H
A0H
C0H
E0H
FFH
feedback reference data byte
(1) (2) (3) (4) (5)
Control bit FPOL = 0. Control bits FPOL = 1, BLH2 = 1, BLH1 = 1. Control bits FPOL = 1, BLH2 = 1, BLH1 = 0. Control bits FPOL = 1, BLH2 = 0, BLH1 = 1. Control bits FPOL = 1, BLH2 = 0, BLH1 = 0.
Fig.12 Internal feedback reference voltages.
handbook, full pagewidth
MHB193
5.77
(1)
external reference voltage (V) 4.05
0 00H
20H
40H
60H
80H
A0H
C0H
E0H
FFH
feedback reference data byte (1) Control bit FPOL = 1.
Fig.13 External feedback reference voltages.
1998 Dec 04
26
Philips Semiconductors
Product specification
140 MHz video controller with I2C-bus
11 I2C-BUS PROTOCOL Table 1 Slave address A5(1) 0 A4(1) 0 A3(1) 0 A2(1) 1 A1(1) 0 A0(1) 0
TDA4886A
A6(1) 1 Notes 1. Address bit. 2. Write bit. Table 2 S(1) Notes
W(2) 0
Slave receiver format SLAVE ADDRESS A(2) SUBADDRESS A(3) DATA BYTE A(4) P(5)
1. START condition. 2. A = acknowledge. 3. All subaddresses within the range 00H to 09H are automatically incremented. The subaddress counter wraps around from 09H to 00H. For subaddresses within the range 80H to 8FH no auto-increment takes place. Subaddresses outside the ranges 00H to 0FH and 80H to 8FH are acknowledged by the device but neither auto-increment nor any other internal operation takes place. 4. Single data byte in case of no auto-increment of subaddresses. More than one data byte with auto-increment of subaddresses. 5. STOP condition.
1998 Dec 04
27
Philips Semiconductors
Product specification
140 MHz video controller with I2C-bus
Table 3 Subaddress byte format SUBADDRESS(1) FUNCTION Control register Brightness control Contrast control OSD contrast control Gain control channel 1 Gain control channel 2 Gain control channel 3 Black level reference channel 1 Black level reference channel 2 Black level reference channel 3 DIRECT MODE 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H
TDA4886A
SUBADDRESS BYTE
BUFFERED S7(2) S6(2) S5(2) S4(2) S3(2) S2(2) S1(2) S0(2) MODE 80H 81H 82H 83H 84H 85H 86H 87H 88H 89H B(3) B(3) B(3) B(3) B(3) B(3) B(3) B(3) B(3) B(3) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 0 1 0 1
0AH to 0FH 8AH to 8FH not used Notes 1. The most significant bit (MSB) of the subaddress enables an I2C-bus transmission in direct or in buffered mode (see note 3). Subaddresses outside the ranges 00H to 0FH and 80H to 8FH are not used. 2. Subaddress bit. 3. Most significant bit of subaddress byte. I2C-bus transmission in direct mode: B = 0. I2C-bus transmission in buffered mode: B = 1.
1998 Dec 04
28
Philips Semiconductors
Product specification
140 MHz video controller with I2C-bus
Table 4 Subaddress and data byte format SUBADDRESS(1) FUNCTION Control register Brightness control Contrast control OSD contrast control Gain control channel 1 Gain control channel 2 Gain control channel 3 Black level reference channel 1 Black level reference channel 2 Black level reference channel 3 Notes 1. See Table 3 (Subaddress byte format). 2. The least significant bit (LSB) of an analog alignment register is defined as AX0 (data bit D0). DIRECT BUFFERED D7(4) D6(4) D5(4) MODE MODE 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 80H 81H 82H 83H 84H 85H 86H 87H 88H 89H X(5) X(5) X(5) X(5) X(5) X(5) X(5) A77 A87 A97 X(5) X(5) X(5) X(5) X(5) X(5) X(5) A76 A86 A96 A15 A25 X(5) A45 A55 A65 A75 A85 A95 DATA BYTE(2) D4(4) D3(4) D2(4) D1(4)
TDA4886A
D0(4)
NOMINAL VALUE(3) 08H 10H 26H 0FH 3FH 3FH 3FH - - -
BLH2 BLH1 FPOL DISV DISO PEDST A14 A24 X(5) A44 A54 A64 A74 A84 A94 A13 A23 A33 A43 A53 A63 A73 A83 A93 A12 A22 A32 A42 A52 A62 A72 A82 A92 A11 A21 A31 A41 A51 A61 A71 A81 A91 A10 A20 A30 A40 A50 A60 A70 A80 A90
3. Under certain conditions the nominal values lead to nominal colour signals etc. (see note 3 of Chapter "Characteristics"). After power-up and after internal power-on reset of the I2C-bus the registers are set to the following values: a) Control bit FPOL to logic 1. b) Control bits BLH2, BLH1, DISV, DISO and PEDST to logic 0. c) All other alignment registers to logic 0 (minimum value for control registers). 4. Data bit. 5. X means don't care but for software compatibility with other video ICs with the same slave address, they are preferably set to logic 0.
1998 Dec 04
29
Philips Semiconductors
Product specification
140 MHz video controller with I2C-bus
Table 5 Control register BIT PEDST = 0 PEDST = 1 DISO = 0 DISO = 1 DISV = 0 DISV = 1 FPOL = 0 FPOL = 1 BLH2 = 0 BLH2 = 0 BLH2 = 1 BLH2 = 1 BLH1 = 0 BLH1 = 1 BLH1 = 0 BLH1 = 1 no pedestal blanking pedestal blanking enabled OSD signals enabled OSD signals disabled video signals enabled video signals disabled FUNCTION
TDA4886A
negative feedback polarity; pins 23, 20 and 17 as external feedback inputs; no external feedback reference voltages positive feedback polarity; pins 23, 20 and 17 as external reference voltage outputs; internal feedback of signal outputs for positive feedback polarity only: internal feedback reference voltage switched to approximately 0.75 V for positive feedback polarity only: internal feedback reference voltage switched to approximately 1.0 V for positive feedback polarity only: internal feedback reference voltage switched to approximately 1.25 V for positive feedback polarity only: internal feedback reference voltage switched to approximately 1.5 V
1998 Dec 04
30
Philips Semiconductors
Product specification
140 MHz video controller with I2C-bus
TDA4886A
handbook, full pagewidth
START
LOAD PRESET CONTROL BITS FPOL PEDST DISV = 1 DISO = 1 BLH2 BLH1
load from program ROM code or EEPROM
LOAD FACTORY SETTINGS GAIN (CHANNEL 1, 2, 3) FEEDBACK REFERENCES (CHANNEL 1, 2, 3) load from EEPROM
LOAD USER PRESET VALUES CONTRAST BRIGHTNESS OSD CONTRAST load from EEPROM
DEFLECTION CONTROL IC LOCKED yes DISV = 0 DISO = 0 DISPLAY NEW MODE(1) DISO = 1
no
USER INPUT
no
yes DISO = 0 RESPONSE TO USER INPUTS(2) (CONTRAST, BRIGHTNESS, OSD CONTRAST) DISO = 1
(1) Only synchronized video should be displayed. Each new mode can be displayed by OSD. (2) Data transmission should be synchronized with vertical blanking of the monitor.
DEFLECTION CONTROL IC LOCKED yes
no DISV = 1
MHB194
Fig.14 I2C-bus control flow.
1998 Dec 04
31
Philips Semiconductors
Product specification
140 MHz video controller with I2C-bus
12 TEST AND APPLICATION INFORMATION
handbook, full pagewidth
TDA4886A
contrast modulation input
limiting input
subcontrast setting fast blanking 1 24 Application with integated post amplifier, DC-coupled cathode and negative feedback. to cathode 90 V 4 21 BLACK LEVEL RESTORATION to cathode Application with integated post amplifier, AC-coupled cathode and black level restoration cicuit.
2 OSD inputs
23
3
22
5
20
6
19
TDA4886A
7 18
70 V
8
17
9
16
90 V
10
15
11
14
Application with discrete post amplifier, DC-coupled cathode and negative feedback. to cathode
12
13
8V
pull-up resistors I2C-BUS
5V
MHB266
output clamping blanking input clamping vertical blanking
Fig.15 Basic applications for different kinds of post amplifiers with DC or AC coupling.
12.1
Test boards
For high frequency measurements a special test application and printed-circuit board with only a few external components is built. It utilizes the internal positive feedback of the output signals during output clamping with control bit FPOL = 1. Figure 16 shows the test application 1998 Dec 04 32
circuit and Figs 17 and 18 show the layout and mounting of the double-sided printed-circuit board. Most components are of SMD type. Short HF loops and minimum crosstalk between the channels and between signal inputs and outputs are achieved by properly shaped ground areas.
Philips Semiconductors
Product specification
140 MHz video controller with I2C-bus
TDA4886A
handbook, full pagewidth
1 k
5.6 FBL FBL 50 OSD1 50 OSD2 50 OSD3 50 CLI 50 10 nF VI1 50 150 pF 5 k J1 10 nF VI2 50 150 pF 5 k J2 10 nF VI3 50 150 pF 5 k J3 HFB 50 150 pF 10 nF SDA 12 13 SCL HFB 11 14 GNDX VI3 10 15 VP3 150 pF 100 nF 5.6 0.47 F (63 V) GND 9 16 VO3 3.3 pF 10 k 0.47 F (63 V) 100 nF 100 pF VI2 8 17 FB/R3 channel 3 VO3 VP 7 VI1 6 19 VO2 3.3 pF 18 VP2 150 pF 100 nF 5.6 0.47 F (63 V) FB/R3 solder pin 10 k 1 24 LIM
OSD1
2
23
FB/R1 channel 1
FB/R1 solder pin
OSD2
3
22
VO1 1 k VP1 150 pF 100 nF 5.6 0.47 F (63 V) FB/R2 3.3 pF 10 k
VO1
OSD3
4
21
CLI
5
20
FB/R2
solder pin channel 2 VO2
TDA4886A
10 nF LIMAC 50 10 k SDA 5V SCL
MHB267
VPX VP1 sense 10 k VP sense 10 nF 10 k VINDC LIM 5V VP GND
Fig.16 Test board utilizing internal positive feedback only (FPOL = 1).
1998 Dec 04
33
Philips Semiconductors
Product specification
140 MHz video controller with I2C-bus
TDA4886A
handbook, full pagewidth
103
81
CLI
OSD3
50 50
OSD2
50
OSD1
50
FBL
10 k
5.6 1 k
50
50 3.3 pF
VO1
150 pF 0.47 F 5.6
VI1
10 nF
10 nF 150 pF 5 k
100 nF
- +
1 k
U19
10 k 3.3 pF
VI2
50 150 pF 5 k 50 10 nF 5 k
J1 J2
0.47 F
VO2 TDA4886A
100 nF 10 k 150 pF
+
- 0.47 F + - 0.47 F +
5.6
VI3
-
150 pF
J3
3.3 pF 100 nF 50 10 nF 150 pF 10 k 10 nF
VO3
HFB
5.6
50
10 k
10 k
SDA
SCL LIMAC
MHB268
Dimensions are in mm.
Fig.17 Top view of the printed-circuit board (for the bottom view see Fig.18).
1998 Dec 04
34
Philips Semiconductors
Product specification
140 MHz video controller with I2C-bus
TDA4886A
handbook, full pagewidth
103
81
100 pF 100 nF
100 nF 100 pF
MHB217
Dimensions are in mm.
Fig.18 Bottom view of the printed-circuit board (for the top view see Fig.17).
1998 Dec 04
35
Philips Semiconductors
Product specification
140 MHz video controller with I2C-bus
12.2 Recommendations for building the application board
TDA4886A
* General - Double-sided board - Short HF loops by large ground plane on the rear - SMD components with minimum parasitics. * Voltage outputs - Capacitive loads as small as possible - Be aware of internal output resistance (typically 75 ). * Supply voltages - Capacitors as near as possible to the pins - Use electrolytic capacitors with small serial resistance and inductance.
1998 Dec 04
36
This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 1998 Dec 04 37 3 OSD2; OSD input channel 2 open-circuit base
5V VP 3 1 k VP 50 A 0V
MHA653
Philips Semiconductors
13 INTERNAL CIRCUITRY
140 MHz video controller with I2C-bus
PIN 1
SYMBOL AND DESCRIPTION FBL; fast blanking input for OSD insertion
CHARACTERISTIC open-circuit base
WAVEFORM
5V VP 0V
MHA653
EQUIVALENT CIRCUIT
50 A signal blanking 1 1 k 50 A OSD1 blanking 50 A OSD2 blanking 50 A OSD3 blanking
MHA928
2
OSD1; OSD input channel 1
open-circuit base
5V VP 2 1 k
VP 50 A signal blanking
0V
MHA653
disable OSD
1 k FBL
MHB197
signal blanking
disable OSD
1 k FBL
MHB198
Product specification
TDA4886A
This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 1998 Dec 04 38
5
Philips Semiconductors
PIN 4
SYMBOL AND DESCRIPTION OSD3; OSD input channel 3
140 MHz video controller with I2C-bus
CHARACTERISTIC open-circuit base
WAVEFORM
5V VP 4
EQUIVALENT CIRCUIT
VP 50 A signal blanking 1 k disable OSD
0V
MHA653
1 k FBL
MHB199
5
CLI; vertical blanking input (input clamping)
V5 > 0.2 V: open-circuit base V5 0.2 V: source current rising with decreasing voltage
MHA651
5V 2.5 V 0V
2VBE 6 k
VP 10 k
26 A
3 V + VBE VP
1 k 10 k power on/down
MHA619
Product specification
TDA4886A
This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 1998 Dec 04 39 Philips Semiconductors PIN 6 SYMBOL AND DESCRIPTION VI1; signal input channel 1
140 MHz video controller with I2C-bus
CHARACTERISTIC outside clamping pulse: open-circuit base with base current compensation during clamping: -135 to +135 A
WAVEFORM
4.7 V black shoulder video signal sync 4V 3.7 V 6
EQUIVALENT CIRCUIT
MIRROR 1:1 VP
VP
input clamping (pin 5)
MHA652
700 1.8 V + VBE signal 135 A 0 A
MHB200
240 A
220 A
7
VP; supply voltage
21 mA
7
MHA621
Product specification
TDA4886A
This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 1998 Dec 04 40 10 VI3; signal input channel 3 outside clamping pulse: open-circuit base with base current compensation during clamping: -135 to +135 A
4.7 V black shoulder video signal sync 4V 3.7 V 10 VP input clamping (pin 5)
MHA652
Philips Semiconductors
PIN 8
SYMBOL AND DESCRIPTION VI2; signal input channel 2
140 MHz video controller with I2C-bus
CHARACTERISTIC outside clamping pulse: open-circuit base with base current compensation during clamping: -135 to +135 A
WAVEFORM
4.7 V black shoulder video signal sync 4V 3.7 V 8
EQUIVALENT CIRCUIT
MIRROR 1:1 VP
VP
input clamping (pin 5)
MHA652
700 1.8 V + VBE signal 135 A 0 A
MHB201
240 A
220 A
9
GND; ground
9
MHA623
MIRROR 1:1
VP
700 1.8 V + VBE signal
Product specification
TDA4886A
135 A 0 A
240 A
220 A
MHB202
This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 1998 Dec 04 41 13 SCL; I2C-bus clock input Philips Semiconductors PIN 11 SYMBOL AND DESCRIPTION HFB; horizontal flyback input (output clamping, blanking)
140 MHz video controller with I2C-bus
CHARACTERISTIC V11 > 0.2 V: open-circuit base V11 0.2 V: source current rising with decreasing voltage
WAVEFORM
5V 0V
MHA649
EQUIVALENT CIRCUIT
2VBE 6 k VP 10 k 27 A clamping 27 A blanking 12 k
VP
3 V + VBE 1 k
1.7 V 10 k
11
power on/down
MHA625
12
SDA; I2C-bus serial data input/output
no acknowledge: open-circuit base during acknowledge: I12 = 4 mA
5V 0V
MHA647
3 A
70 A
19 A
10 k 12
2.46 V + VBE
acknowledge
MHB203
open-circuit base
5V 0V
MHA648
19 A 10 k 13
Product specification
TDA4886A
2.46 V + VBE
MHB204
This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 1998 Dec 04 42 control bit PEDST = 0 pedestal black level 0.1 to 2.8 V
brightness
MHB207 MHA656
Philips Semiconductors
PIN 14
SYMBOL AND DESCRIPTION GNDX; signal channel ground
140 MHz video controller with I2C-bus
CHARACTERISTIC
WAVEFORM
EQUIVALENT CIRCUIT
14
MHB205
15
VP3; supply voltage channel 3
I15 = 21 mA
15
MHB206
16
VO3; signal reference black level output channel 3 0.1 to 2.8 V
brightness
MHA655
VP VP 500
16 reference black level during output clamping
75
8 k 1.5 k
1 k
3.5 pF 10 A
pedestal black level during output clamping
control bit PEDST = 1 Product specification
TDA4886A
This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 1998 Dec 04 43
1 k 5.77 to 4.05 V
Philips Semiconductors
PIN 17
SYMBOL AND DESCRIPTION FB/R3; feedback input/ reference voltage output channel 3
140 MHz video controller with I2C-bus
CHARACTERISTIC open-circuit base
WAVEFORM
feedback reference 5.77 to 4.05 V VP
EQUIVALENT CIRCUIT
40 I PEDST = 0 PEDST = 1
MHB215
2I
17
100 5.77 to 4.05 V
1 k
control bit FPOL = 0 -300 to +300 A; 5.77 to 4.05 V control bit FPOL = 1
3 k I
10 A
10 A
15 k Vs1 15 k Vs2
MHB208
DC coupling; Vs1 = 0 V; Vs2 = 1 V; I = 0 (control bit FPOL = 0) AC coupling; Vs1 = 1 V; Vs2 = 0 V; I = 7.5 A (control bit FPOL = 1)
18
VP2; supply voltage channel 2
I18 = 21 mA
18
Product specification
TDA4886A
MHB218
This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 1998 Dec 04 44 control bit PEDST = 1 Philips Semiconductors PIN 19 SYMBOL AND DESCRIPTION
140 MHz video controller with I2C-bus
CHARACTERISTIC
WAVEFORM
MHA655
EQUIVALENT CIRCUIT
VP VP 500
reference black level VO2; signal output channel 2 0.1 to 2.8 V
brightness
19 reference black level during output clamping
75
8 k 1.5 k
1 k
3.5 pF 10 A
control bit PEDST = 0 pedestal black level 0.1 to 2.8 V
brightness
MHB209 MHA656
pedestal black level during output clamping
Product specification
TDA4886A
This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 1998 Dec 04 45
1 k 5.77 to 4.05 V
Philips Semiconductors
PIN 20
SYMBOL AND DESCRIPTION FB/R2; feedback input/ reference voltage output channel 2
140 MHz video controller with I2C-bus
CHARACTERISTIC open-circuit base
WAVEFORM
feedback reference 5.77 to 4.05 V VP
EQUIVALENT CIRCUIT
40 I PEDST = 0 PEDST = 1
MHB215
2I
20
100 5.77 to 4.05 V
1 k
control bit FPOL = 0 -300 to +300 A; 5.77 to 4.05 V control bit FPOL = 1
3 k I
10 A
10 A
15 k Vs1 15 k Vs2
MHB210
DC coupling; Vs1 = 0 V; Vs2 = 1 V; I = 0 (control bit FPOL = 0) AC coupling; Vs1 = 1 V; Vs2 = 0 V; I = 7.5 A (control bit FPOL = 1)
21
VP1; supply voltage channel 1
I21 = 21 mA
21
Product specification
TDA4886A
MHB211
This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 1998 Dec 04 46 control bit PEDST = 1 Philips Semiconductors PIN 22 SYMBOL AND DESCRIPTION
140 MHz video controller with I2C-bus
CHARACTERISTIC
WAVEFORM
MHA655
EQUIVALENT CIRCUIT
VP VP 500
reference black level VO1; signal output channel 1 0.1 to 2.8 V
brightness
22 reference black level during output clamping
75
8 k 1.5 k
1 k
3.5 pF 10 A
control bit PEDST = 0 pedestal black level 0.1 to 2.8 V
brightness
MHB212 MHA656
pedestal black level during output clamping
Product specification
TDA4886A
This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 1998 Dec 04 47
1 k 5.77 to 4.05 V
Philips Semiconductors
PIN 23
SYMBOL AND DESCRIPTION FB/R1; feedback input/ reference voltage output channel 1
140 MHz video controller with I2C-bus
CHARACTERISTIC open-circuit base
WAVEFORM
feedback reference 5.77 to 4.05 V VP
EQUIVALENT CIRCUIT
40 I PEDST = 0 PEDST = 1
MHB215
2I
23
100 5.77 to 4.05 V
1 k
control bit FPOL = 0 -300 to +300 A; 5.77 to 4.05 V control bit FPOL = 1
3 k I
10 A
10 A
15 k Vs1 15 k Vs2
MHB213
DC coupling; Vs1 = 0 V; Vs2 = 1 V; I = 0 (control bit FPOL = 0) AC coupling; Vs1 = 1 V; Vs2 = 0 V; I = 7.5 A (control bit FPOL = 1)
Product specification
TDA4886A
This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 1998 Dec 04 48 Philips Semiconductors PIN 24 SYMBOL AND DESCRIPTION LIM; beam current limiting input
140 MHz video controller with I2C-bus
CHARACTERISTIC open-circuit voltage V24 = 5.0 V V24 < 4.5 V: open-circuit base
WAVEFORM
VP
EQUIVALENT CIRCUIT
21 A 1 k 5.0 V 10 k
24
MHB214
Product specification
TDA4886A
Philips Semiconductors
Product specification
140 MHz video controller with I2C-bus
14 PACKAGE OUTLINE SDIP24: plastic shrink dual in-line package; 24 leads (400 mil)
TDA4886A
SOT234-1
D seating plane
ME
A2
A
L
A1 c Z e b 24 13 b1 wM (e 1) MH
pin 1 index E
1
12
0
5 scale
10 mm
DIMENSIONS (mm are the original dimensions) UNIT mm Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT234-1 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION A max. 4.7 A1 min. 0.51 A2 max. 3.8 b 1.3 0.8 b1 0.53 0.40 c 0.32 0.23 D (1) 22.3 21.4 E (1) 9.1 8.7 e 1.778 e1 10.16 L 3.2 2.8 ME 10.7 10.2 MH 12.2 10.5 w 0.18 Z (1) max. 1.6
ISSUE DATE 92-11-17 95-02-04
1998 Dec 04
49
Philips Semiconductors
Product specification
140 MHz video controller with I2C-bus
15 SOLDERING 15.1 Introduction to soldering through-hole mount packages
TDA4886A
The total contact time of successive solder waves must not exceed 5 seconds. The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (Tstg(max)). If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. 15.3 Manual soldering
This text gives a brief insight to wave, dip and manual soldering. A more in-depth account of soldering ICs can be found in our "Data Handbook IC26; Integrated Circuit Packages" (document order number 9398 652 90011). Wave soldering is the preferred method for mounting of through-hole mount IC packages on a printed-circuit board. 15.2 Soldering by dipping or by solder wave
The maximum permissible temperature of the solder is 260 C; solder at this temperature must not be in contact with the joints for more than 5 seconds. 15.4
Apply the soldering iron (24 V or less) to the lead(s) of the package, either below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300 C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 and 400 C, contact may be up to 5 seconds.
Suitability of through-hole mount IC packages for dipping and wave soldering methods SOLDERING METHOD PACKAGE DIPPING WAVE suitable(1)
DBS, DIP, HDIP, SDIP, SIL Note
suitable
1. For SDIP packages, the longitudinal axis must be parallel to the transport direction of the printed-circuit board.
1998 Dec 04
50
Philips Semiconductors
Product specification
140 MHz video controller with I2C-bus
16 DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values
TDA4886A
This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. 17 LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. 18 PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011.
1998 Dec 04
51
Philips Semiconductors - a worldwide company
Argentina: see South America Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. +61 2 9805 4455, Fax. +61 2 9805 4466 Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213, Tel. +43 160 1010, Fax. +43 160 101 1210 Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6, 220050 MINSK, Tel. +375 172 200 733, Fax. +375 172 200 773 Belgium: see The Netherlands Brazil: see South America Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor, 51 James Bourchier Blvd., 1407 SOFIA, Tel. +359 2 689 211, Fax. +359 2 689 102 Canada: PHILIPS SEMICONDUCTORS/COMPONENTS, Tel. +1 800 234 7381 China/Hong Kong: 501 Hong Kong Industrial Technology Centre, 72 Tat Chee Avenue, Kowloon Tong, HONG KONG, Tel. +852 2319 7888, Fax. +852 2319 7700 Colombia: see South America Czech Republic: see Austria Denmark: Prags Boulevard 80, PB 1919, DK-2300 COPENHAGEN S, Tel. +45 32 88 2636, Fax. +45 31 57 0044 Finland: Sinikalliontie 3, FIN-02630 ESPOO, Tel. +358 9 615800, Fax. +358 9 61580920 France: 51 Rue Carnot, BP317, 92156 SURESNES Cedex, Tel. +33 1 40 99 6161, Fax. +33 1 40 99 6427 Germany: Hammerbrookstrae 69, D-20097 HAMBURG, Tel. +49 40 23 53 60, Fax. +49 40 23 536 300 Greece: No. 15, 25th March Street, GR 17778 TAVROS/ATHENS, Tel. +30 1 4894 339/239, Fax. +30 1 4814 240 Hungary: see Austria India: Philips INDIA Ltd, Band Box Building, 2nd floor, 254-D, Dr. Annie Besant Road, Worli, MUMBAI 400 025, Tel. +91 22 493 8541, Fax. +91 22 493 0966 Indonesia: PT Philips Development Corporation, Semiconductors Division, Gedung Philips, Jl. Buncit Raya Kav.99-100, JAKARTA 12510, Tel. +62 21 794 0040 ext. 2501, Fax. +62 21 794 0080 Ireland: Newstead, Clonskeagh, DUBLIN 14, Tel. +353 1 7640 000, Fax. +353 1 7640 200 Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053, TEL AVIV 61180, Tel. +972 3 645 0444, Fax. +972 3 649 1007 Italy: PHILIPS SEMICONDUCTORS, Piazza IV Novembre 3, 20124 MILANO, Tel. +39 2 6752 2531, Fax. +39 2 6752 2557 Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku, TOKYO 108-8507, Tel. +81 3 3740 5130, Fax. +81 3 3740 5077 Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL, Tel. +82 2 709 1412, Fax. +82 2 709 1415 Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR, Tel. +60 3 750 5214, Fax. +60 3 757 4880 Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905, Tel. +9-5 800 234 7381 Middle East: see Italy Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB, Tel. +31 40 27 82785, Fax. +31 40 27 88399 New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND, Tel. +64 9 849 4160, Fax. +64 9 849 7811 Norway: Box 1, Manglerud 0612, OSLO, Tel. +47 22 74 8000, Fax. +47 22 74 8341 Pakistan: see Singapore Philippines: Philips Semiconductors Philippines Inc., 106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI, Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474 Poland: Ul. Lukiska 10, PL 04-123 WARSZAWA, Tel. +48 22 612 2831, Fax. +48 22 612 2327 Portugal: see Spain Romania: see Italy Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW, Tel. +7 095 755 6918, Fax. +7 095 755 6919 Singapore: Lorong 1, Toa Payoh, SINGAPORE 319762, Tel. +65 350 2538, Fax. +65 251 6500 Slovakia: see Austria Slovenia: see Italy South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale, 2092 JOHANNESBURG, P.O. Box 7430 Johannesburg 2000, Tel. +27 11 470 5911, Fax. +27 11 470 5494 South America: Al. Vicente Pinzon, 173, 6th floor, 04547-130 SAO PAULO, SP, Brazil, Tel. +55 11 821 2333, Fax. +55 11 821 2382 Spain: Balmes 22, 08007 BARCELONA, Tel. +34 93 301 6312, Fax. +34 93 301 4107 Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM, Tel. +46 8 5985 2000, Fax. +46 8 5985 2745 Switzerland: Allmendstrasse 140, CH-8027 ZURICH, Tel. +41 1 488 2741 Fax. +41 1 488 3263 Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1, TAIPEI, Taiwan Tel. +886 2 2134 2865, Fax. +886 2 2134 2874 Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd., 209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260, Tel. +66 2 745 4090, Fax. +66 2 398 0793 Turkey: Talatpasa Cad. No. 5, 80640 GULTEPE/ISTANBUL, Tel. +90 212 279 2770, Fax. +90 212 282 6707 Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7, 252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461 United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes, MIDDLESEX UB3 5BX, Tel. +44 181 730 5000, Fax. +44 181 754 8421 United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409, Tel. +1 800 234 7381 Uruguay: see South America Vietnam: see Singapore Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD, Tel. +381 11 625 344, Fax.+381 11 635 777 Internet: http://www.semiconductors.philips.com
For all other countries apply to: Philips Semiconductors, International Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 (c) Philips Electronics N.V. 1998
SCA60
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
545104/00/01/pp52
Date of release: 1998 Dec 04
Document order number:
9397 750 04817

▲Up To Search▲

Price & Availability of TDA4886A

	To Download TDA4886A Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .